1. Field of the Invention
The invention relates to an integrated circuit device and, more particularly, to an integrated circuit device in which a cylindrical structure made up of carbon atoms is used as a material for a wiring member or a material for a via interconnecting wiring lines located in separate layers.
Also, the present invention relates to a semiconductor device, and in particular to a semiconductor device of a new type made up of a cylindrical multilayer structure or, typically, a new material called carbon nanotube.
Further, the present invention relates to a transistor, and in particular to a field effect transistor made of carbon nanotubes having metallic characteristics used as a gate material.
Furthermore, the present invention relates to a method of forming a micro pattern using carbon nanotubes as a masking material for dry etching.
2. Description of the Related Art
A half of a century has passed since the invention of the transistor, and remarkable progress has been made in semiconductor integrated circuits (semiconductor ICs) developed based on transistor technology, leading to large scale integrated circuits (LSIs) having ever greater integrity. With a current LSI, a phenomenon of movement of a metal atom of a wiring material, which is known as a migration phenomenon, is noted as a factor in loss of reliability of the LSI. This phenomenon can result in the breaking of a wiring line caused by stresses on the wiring metal material or electrons passing through the wiring line, and, in most cases, occurs particularly at a via for interconnecting wiring lines which must take a complex structure. The migration caused by stress is called stress migration, and that caused by electrons passing through a wiring is called electro-migration.
As a wiring material, copper (Cu) has recently started to be used in place of conventional aluminum (Al). Although the use of copper improves the migration resistance of a wiring to some extent, it is said that the migration resistance of a wiring line of copper, represented by a current density, is at most of the order of up to 105 amperes per square centimeter. This critical value for the migration resistance has intimate relation to the capacity of heat dissipation of a wiring line, and it is known that the critical value is lowered in the case of poor heat dissipation or increased temperature.
On the other hand, providing semiconductor ICs having increased performance has been done according to the scaling rule of transistors. This approach would reach its limit sooner or later due to factors such as a limit of lithography technique. As a method for overcoming the limit of lithography technique, there is a technique of forming a fine structure using self-organizing. Currently, quantum dot devices and molecular devices using self-organizing, which are generally termed nano-devices, are energetically studied and, to enter an era in which such nano-devices are used as components in integrated circuits, wiring techniques for these devices must also be developed in parallel. Otherwise, the integrity of the nano-device is also forced to be determined by the limit of wiring technique.
On the other hand, since the invention of the transistor, it has progressed with various improvements. Taking as an example, the field effect transistor in which the channel region located between two regions including the source and the drain is formed as a current path of carriers and the electrical resistance of this channel is changed by the voltage of the gate electrode thereby to control the current flowing in the channel region, to meet the requirement of operation at higher speed and higher frequency, the gate length has been reduced and the carrier mobility of the channel material has increased greatly. The gate length has already been reduced to the order of 10 nm, which has posed many problems including the deteriorated matching accuracy due to fluctuations in lithography, an increased turn-off current of the transistor (short channel effect), a turn-on current saturation and an increased gate leakage current. Achieving a high dielectric constant of the gate insulating film has been studied as reliable means for solving some of these problems. On the other hand, an approach to improved current controlability of the gate has been conceived of by changing the gate structure of the transistor from the planar type currently employed to the three-dimensional type (e.g., what is called the surround gate structure).
In the surround gate structure, as shown in FIG. 9, a semiconductor channel layer (a p-type semiconductor layer in the case under consideration) 301 is surrounded by a gate electrode 302 like a coaxial cable. In this structure, the electric lines of force extending from the gate are prevented from escaping out of the channel, and therefore the current control efficiency is higher than that of the gate structure of planar type, thereby making a promising candidate for suppressing the short channel effect. In the semiconductor device shown in FIG. 9, reference numeral 303 designates a source electrode, numeral 304 a drain electrode, numeral 305 a high-concentration n-type semiconductor layer buried in a semiconductor substrate 309 for connecting the source electrode 303 and the channel 301, numeral 306 a high-concentration n-type semiconductor layer for connecting the drain electrode 304 and the channel 301, and numeral 307 an insulating material.
Nevertheless, the surround gate structure requires a cylindrical semiconductor layer extending upward of the substrate surface, which cannot be easily fabricated. For this reason, many problems still remain to be solved. For example, the threshold voltage (the gate voltage for turning off the current flowing in the transistor) is liable to vary from one transistor to another, and the control of impurities concentration by doping is difficult.
The various problems including the aforementioned ones are inherent to the conventional field effect transistors, or especially, those extremely micronized, and are a stumbling block to the development of a field effect transistor having superior characteristics which have yet to be realized.
Higher density of the semiconductor LSI has been promoted by the micro-fabrication technique of component semiconductor elements and wires. In the micro-fabrication of the semiconductor LSI, the first step is to etch a substrate using a resist patterned by lithography as a mask. A high resolution and a high etching durability are the characteristics required of the resist. In the conventional organic polymer resist, however, a pattern of the order of 10 nm, which is smaller than the polymer molecule, cannot be resolved. Also, insufficient resistance of the resist to dry etching makes it necessary to transfer the pattern to another film for etching.
The shortest gate length of the transistor so far reported is 8 nm for a transistor having a MOS structure fabricated by electron beam exposure. Since the resolution of the resist has almost reached a limit, however, the gate formed by this method has large gate size fluctuations and inferior linearity. This gate, therefore, is not suitable for practical applications. Generally, the reduction of gate length contributes most effectively to an improved high-speed and high-frequency performance of the transistor. Therefore, a technique for matching the gate to 10 nm or less with minimum fluctuations which replaces the use of resist is in great demand.
A HEMT (high electron mobility transistor) fabricated on an InP substrate is currently known as a high-frequency transistor of the highest performance. The HEMT of the highest performance reported by A. Endoh, et al. has a gate length of 25 nm with a cut-off frequency fT as high as about 400 GHz (A. Endoh et al., IPRM '01, pp.448–451 (2001)). with regard to the high-speed optical communication network, on the other hand, the TDM system having a communication speed of 40 Gbps is under development. As a future system, however, a communication speed of 160 Gbps is desired (FIG. 23). In such a case, the frequency fT four to five times as high as the communication speed is generally required as the characteristics of the electronic devices for communication of an optical modulation system. For the communication speed of 160 Gbps, for example, it is predicted that the frequency fT of 640 to 800 GHz is required. A certain correlationship is known between the frequency fT and the gate length of an electronic device, and is plotted as a graph in FIG. 24. In FIG. 24, the relation between the gate length so far realized and the corresponding frequency fT (the range indicated by solid line in FIG. 24) is extrapolated. It is thus seen that a gate length of less than 10 nm is required for obtaining the frequency fT of about 800 GHz. In this way, further reduction of the gate length is essential to meet the requirement of high-speed communication in the foreseeable future.